1. Field of the Invention
The present invention generally relates to a bit synchronizing circuit used in a communication appliance. More specifically, the present invention is directed to a bit synchronizing circuit having a high synchronization characteristic utilized in, for example, a paging receiver.
2. Description of the Related Art
Various types of paging receivers are commercially available. For instance, in a paging receiver capable of receiving a "POCSAG(Post Office Code Standardization Advisory Group)" type paging signal, i.e., the FSK(Frequency Shift Keying) modulation type paging signal, the received FSK signal is converted into a binary signal of NRZ(Non Return to Zero), and further this NRZ binary signal is converted into digital data by reading as to whether the level of this NRZ binary signal is the high level, or the low level. To correctly convert the FSK signal into the digital data (namely, data demodulation), the above-described level judgment of the binary signal is preferably carried out near center points within the respective bit periods (namely, duration time period of 1-bit data). To realize the correct data demodulation, a bit synchronizing circuit is employed by which the generation timing of the data sampling pulse is synchronized with the bit of the received data. A typical bit synchronizing circuit is shown in FIG. 1.
In this conventional bit synchronizing circuit, reference numeral 1 shows an edge detector for detecting an edge of a waveform (namely, a changing point of a waveform) of an input signal (namely, an NRZ signal obtained from a received FSK signal) is detected, and then for outputting a detection pulse. The detection pulse outputted from this edge detector 1 is entered into an edge number counter 2, and also another edge number counter 3. The edge number counter 2 counts the number of the detection pulse derived from the edge detector 1 only when a count value of an up/down counter 4 (will be explained later) becomes greater than, or equal to a half count value, and also resets the count value thereof when this count value reaches a preselected value and further sends out an up signal to the up/down counter 4. On the other hand, the other edge number counter 3 counts the number of the detection pulse derived from the edge detector 1 only when a count value of an up/down counter 4 becomes smaller than, or equal to a half count value, and also resets the count value thereof when this count value reaches a preselected value and further sends out a down signal to the up/down counter 4.
The up/down counter 4 executes both the up-counting operation and the down-counting operation in addition to the normal counting operation during which the counting operation is performed one by one in response to the clock "CK" having the clock speed N ("N" being an integer, for example, 16) times higher than the bit rate of the input signal. In the up-counting operation, the counting operation is further performed by 1 count when the up signal is supplied from the edge number counter 2. In the down-counting operation, the normal count-up operation is pulled out by 1 count when the down signal is supplied from the edge number counter 3. This up/down counter 4 may constitute the bit synchronization counter. When the clock speed is N times higher than the bit rate of the input signal, this up/down counter 4 is executes such a counting operation that N counts are set as a 1 cycle. As a result, since the up-counting operation and the down-counting operation are carried out in response to the signals outputted from the edge number counters 2 and 3, the phase is corrected, so that such a bit synchronization signal synchronized with the bit of the input signal can be outputted. Then, normally, when the count value of this up/down counter 4 reaches a half value of the full count value (for example 16), the synchronization pulse is outputted to be supplied as the data sampling pulse to the data demodulating circuit.
In the above-described circuit arrangement, in the case that the count value when the edge number counter 2 outputs the up signal is set to the small value and the count value when the edge number counter 3 outputs the down signal is set to the small value, the count value corrections of the up/down counter 4 frequently occur based on the noise contained in the input signal and the bit data having the deteriorated duty ratio (namely, bit data having bit length longer than normal bit length, or bit data having bit length shorter than normal bit length), which would deteriorate the synchronization stability. Conversely, when the count values of the edge number counters 2 and 3 are set to the large values, although the synchronization stability is increased, there is a problem that the synchronization capture speeds are delayed. In other words, there is such a drawback that lengthy time is necessarily required from the asynchronous condition, for instance, from such a condition occurred just after the power supply of the paging receiver is turned ON until the synchronous condition.
Furthermore, since the above-described conventional bit synchronizing circuit is so arranged as to output the up signal and the down signal when both the edge number counter 2 and the edge number counter 3 count each of predetermined values, even when the count values of the edge number counters 2 and 3 are set to the large values, there is a further problem that the count value corrections of the up/down counter 4 based on the noise contained in the input signal cannot be avoided.